Building a RISC-V CPU from scratch - Part 1

06/08/2022

I've been working on flintRV - a RISC-V CPU from scratch.

Why design/use a CPU from scratch? 🤔

• Full design control over CPU and its implemented instructions and extensions
  • RISC-V is solid choice as it's a modular and open instruction set architecture (ISA)
  • One can also define their own custom CPU instructions (lots of possibilities here)
  • Full control over how simple or complex you want your design to be
• When designing a microcontroller/SoC around your CPU, choose/design the peripherals you want
  • Compared to a microcontroller search to find one that generally fits your requirements
  • Often end up with unused/not-enough peripherals
  • Standard peripheral set might not cut it for niche/custom interface with some component
  • Emulating niche/custom interface over GPIO/bit-banging likely not fast enough either
• SoC or microcontroller CPU micro-architecture can be scaled over time
  • Want to dabble with a multi-core CPU design? Go for it!
  • Enhance the single core performance by adding superscalar or Out-of-Order execution
  • Enhancements even at lower-levels (e.g. different adder/mult/div hardware algorithms)

There are probably more highlights here, but I find these to be the most compelling reasons.

There's also a great talk on this subject on this Hackaday video here - MicroFPGA.

Just one point to make here before continuing - when starting an embedded project that needs some sort of controller, the wise/simple choice would be to consider microcontrollers first over designing and using one's own (or someone elses) CPU design. Often times off-the-shelf ARM Cortex based micros these days already cover a vast range of projects. There's even the popular Raspberry Pi Pico that features 2 Cortex M0+ CPUs, plenty of peripherals - RAM/ROM - I/O, and even a fancy Programmable IO unit (PIO) to flexibly create a new hardware interface.

Design 📊

• Use RISC-V for the core's ISA
  • The ISA is open meaning no licensing fees for custom designs
  • Being a modular ISA, we can start with the base RV32I ISA here (32-bit Integer)
  • Cross-Compiler toolchain is fairly robust at this point - GCC/Clang support, nice!
• Design a 4-stage pipelined soft-cpu
  • Stages being: Fetch/Decode -> Execute -> Memory -> Writeback
  • Simple static branch prediction, dynamic predictors later
  • In-order design for now

The idea for the first-go is to keep things simple, then expand later.

Project Setup 🛠️

Here's the breakdown of the flow I have set-up (for now):

• GNU Make: for the build tool
• Verilator: for converting synthasizable Verilog to a cycle-accurate simulation model
• Python: for scripting and code generating
• riscv64-unknown-elf-gcc: C/C++ cross-compiler
• Docker: for an easy-mode way to contain riscv cross-compiler in a container
• GTKWave: Tool to view signals of simulation runs graphically

Will later explore SymbiYosys, Yosys, and z3 to perform formal verification on certain critical components.